 | ||||||
 |
 |
 |
 |
 |
 |
 |
 | ||||||
 |
 | |||||
|
|
|
|
| THURSDAY, June 10, 2004, 2:00 PM - 4:00 PM | Room: 6B | ||
|
TOPIC AREA: POWER | ||
| SESSION 47 | |||
| Leakage Power Optimization | |||
| Chair: Farid N. Najm - Univ. of Toronto, Toronto , Canada | |||
| Organizers: Enrico Macii, Naehyuck Chang | |||
| This session presents different approaches for reducing leakage power consumption in deep submicron CMOS circuits. The papers investigate different trade-offs between gate Tox, Vdd, Vth and sizing. Also, techniques for deriving input vector control and encoding schemes for simultanous crosstalk and leakage power reduction on buses are described. | |||
 47.1 |
Tradeoffs between Gate Oxide Leakage and Delay for Dual Tox Circuits |
||
| Speaker(s): | Anup Kumar Sultania - Univ. of Minnesota, Minneapolis, MN | ||
| Author(s): | Anup Kumar Sultania - Univ. of Minnesota, Minneapolis, MN Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN | ||
| 47.2 | Implicit Pseudo Boolean Enumeration Algorithms for Input Vector Control | ||
| Speaker(s): | Kaviraj S. Chopra - Univ. of Arizona, Tucson, AZ | ||
| Author(s): | Kaviraj S. Chopra - Univ. of Arizona, Tucson, AZ Sarma Vrudhula - Univ. of Arizona, Tucson, AZ | ||
| 47.3 | Statistical Optimization of Leakage Power Considering Process Variations Using Dual-Vth and Sizing | ||
| Speaker(s): | Ashish Srivastava - Univ. of Michigan, Ann Arbor, MI | ||
| Author(s): | Ashish Srivastava - Univ. of Michigan, Ann Arbor, MI Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI David Blaauw - Univ. of Michigan, Ann Arbor, MI | ||
| 47.4s | Leakage - and Crosstalk-Aware Bus Encoding for Total Power Reduction | ||
| Speaker(s): | Harmander S. Deogun - Univ. of Michigan, Ann Arbor, MI | ||
| Author(s): | Harmander S. Deogun - Univ. of Michigan, Ann Arbor, MI Rajeev R. Rao - Univ. of Michigan, Ann Arbor, MI Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI David Blaauw - Univ. of Michigan, Ann Arbor, MI | ||
| 47.5s | Power Minimization Using Simultaneous Gate Sizing, Dual-Vdd, and Dual-Vth Assignment | ||
| Speaker(s): | Ashish Srivastava - Univ. of Michigan, Ann Arbor, MI | ||
| Author(s): | Ashish Srivastava - Univ. of Michigan, Ann Arbor, MI Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI David Blaauw - Univ. of Michigan, Ann Arbor, MI | ||
 | |||